1. Field of the Invention
The present invention relates to a semiconductor memory device and a bit line sensing method. More particularly, the present invention relates to a semiconductor memory device that may be operated at a low power voltage.
2. Description of the Related Art
In a semiconductor memory device, a charge transfer pre-sensing (CTPS) function is typically used to improve a sensing margin of a lower power voltage.
FIG. 1 illustrates a circuit diagram of a conventional semiconductor memory device having a charge transfer pre-sensing scheme. This conventional semiconductor memory device includes a cell bit line pre-charge circuit 10, a PMOS sense amplifier 12, a sense amplifier bit line pre-charge circuit 16, an NMOS sense amplifier 18, first and second bit line isolation circuits 14 and 20, respectively, and memory cells MCi and MCj.
The memory cell MCi represents a representative memory cell among memory cells arranged in a memory cell array block BLK1 among n-number of memory cell array blocks BLK1 to BLKn. Similarly, memory cell MCj represents a representative memory cell among memory cells arranged in the memory cell array block BLK2. A capacitor Cb1 represents a cell bit line load capacitor, and a capacitor Csa represents a sense amplifier bit line load capacitor.
NMOS transistors N1, N2 and N3 of the cell bit line pre-charge circuit 10 are turned on in response to a control signal BLPRE having a logic xe2x80x9chighxe2x80x9d level to pre-charge the cell bit line pair BLcelli and BLBcelli to a voltage Vcca/2. PMOS transistors P1 and P2 of the PMOS sense amplifier 12 are turned on in response to a voltage of the cell bit line pair BLBcelli and BLcelli having a logic xe2x80x9clowxe2x80x9d level to amplify a voltage of the bit line pair BLcelli and BLBcelli having a logic xe2x80x9chighxe2x80x9d level to a voltage Vcca. NMOS transistors N4 and N5 of the first bit line isolation circuit 14 are turned on in response to a control signal SG1 to electrically connect the cell bit line pair BLcelli and BLBcelli to the sense amplifier bit line pair BLsa and BLBsa, respectively. NMOS transistors N6, N7 and N8 of the sense amplifier bit line pre-charge circuit 16 are turned on in response to a control signal SAPRE having a logic xe2x80x9chighxe2x80x9d level to pre-charge the sense amplifier bit line pair BLsa and BLBsa to a voltage Vcca. NMOS transistors N9 and N10 of the NMOS sense amplifier 18 are turned on in response to a voltage of the sense amplifier bit line pair BLsa and BLBsa having a logic xe2x80x9clowxe2x80x9d level to make the voltage of the sense amplifier bit line pair BLsa and BLBsa a ground voltage. NMOS transistors N11 and N12 of the second bit line isolation circuit 20 are turned on in response to a control signal SG2 to electrically connect the cell bit line pair BLcellj and BLBcellj to the sense amplifier bit line pair BLsa and BLBsa, respectively.
Operation of the semiconductor memory device of FIG. 1 is described below with reference to FIG. 2, in which a timing diagram illustrating an operation of the semiconductor memory device of FIG. 1 is shown. In FIG. 2, a data is read from the memory cell array block BLK, and a cell array voltage Vcca is 0.8 volts.
A pre-charging operation is initiated with the application of the control signals BLPRE, SAPRE, SG1 and SG2. The activating voltage level for SG1 and SG2 is 0 volts. The NMOS transistors N4 and N5 are turned off to electrically separate the sense amplifier bit line pair BLsa and BLBsa from the cell MCi bit line pair BLcelli and BLBcelli, and the NMOS transistors N11 and N12 are turned off to electrically separate the sense amplifier bit line pair BLsa and BLBsa from the cell MCj bit line pair BLcelli and BLBcelli. The NMOS transistors N1 to N3 are turned on to pre-charge the cell bit line pair BLcelli and BLBcelli to a voltage Vcca/2 (=0.4 volts). The NMOS transistors N6, N7 and N8 are turned on to pre-charge the sense amplifier bit line pair BLsa and BLBsa to a voltage Vcca(1+xcex3) (=1.6 volts).
Then, when a read command is applied to select word line WLi, the NMOS transistor NM of the memory cell MCi connected to the word line WLi is turned on, and a charge sharing operation is performed between a capacitor C and the cell bit line pair BLcelli and BLBcelli. This causes a voltage difference xcex94VBLcell to occur between the cell bit line pair.
When the control signal SG1 is activated with a voltage of 0.9 volts, the NMOS transistors N4 and N5 are turned on and a charge transfer operation is performed between the cell bit line pair BLcelli and BLBcelli and the sense amplifier bit line pair BLsa and BLBsa. Hence, a voltage of the sense amplifier bit line pair BLsa and BLBsa is lowered, and a voltage difference occurs between the sense amplifier bit line pair BLsa and BLBsa, as governed by the equation:
xcex94VBLsa(=xcex94Vxc3x97(Cb1+Csa)/Csa).xe2x80x83xe2x80x83[1]
As the voltage of the sense amplifier bit line pair BLsa and BLBsa decreases, the voltage of the cell bit line pair BLcelli and BLBcelli increases, and the voltage difference between the cell bit line pair BLcelli and BLBcelli, xcex94VBLcelli, is steadily lowered to 0 volts. Thereafter, when the voltage difference xcex94VBLsa occurs between the sense amplifier bit line pair BLsa and BLBsa, the PMOS sense amplifier 12 and the NMOS sense amplifier 18 operate to amplify the voltage of the cell bit line BLcelli and the sense amplifier bit line BLsa to Vcca, and the voltage of the cell bit line BLBcelli, and the sense amplifier bit line BLBsa to 0 volts.
However, the semiconductor memory device of FIG. 1 has a problem in that it is difficult to set a level of the control signal SG1, which is governed by the inequality [2]:       1    2    ⁢  Vcca  ⁢      (          1      +              1                  1          +                                    Cb1              +              Cs                        Cs                                ≤          VSG1      -      Vth        ≤                                                      Vcca              ⁢                              (                                  1                  +                  γ                                )                                      ⁢            Csa                    +                                    (                                                1                  2                                ⁢                Vcca                            )                        ⁢            Cb1                                    Cb1          +          Cs          +          Csa                    +      0.05      
where VSG1 denotes a voltage of the control signal SG1 and Vth denotes a threshold voltage of the NMOS transistors N4 and N5.
A left member of the inequality is a lower limit of a voltage of the control signal SG1, and a right member of the inequality is an upper limit of a voltage of the control signal SG1. A voltage of the control signal SG1 is at least higher by a threshold voltage Vth than a data having a logic xe2x80x9chighxe2x80x9d level, and is at least lower by a threshold voltage Vth than a data having a logic xe2x80x9clowxe2x80x9d level. That is, the left member and the right member of the inequality are the upper limit and the lower limit, respectively, when NMOS transistors N4 and N5 operate in a saturation region rather than in a linear region to perform a charge transfer operation.
In order to increase a voltage margin of the control signal SG1, the pre-charge voltage has to be greater than a voltage Vcca with xcex3 having a value of about 1. Assume that the capacitor C has a capacitance of 20 fF, the capacitor Cb1 has a capacitance of 120 fF, the voltage Vcca has a voltage of 0.8 volts, and a threshold voltage has a voltage of 0.4 volts. If the values are substituted in the inequality, the voltage VSG1 of the control signal SG1 is bounded by 0.85 volts or more and 0.95 volts or less. Thus, the voltage VSG1 has a very small margin of 0.1 volts. Therefore, it is very difficult to accurately set a level of the control signal SG1.
In addition, the semiconductor memory device of FIG. 1 has a problem in that the PMOS sense amplifier 12 is not shared between the respective memory cell array blocks but is separately configured, thereby increasing a layout area size. Furthermore, since the sense amplifier bit line pair BLsa and BLBsa have to be pre-charged to be higher than a voltage Vcca during the pre-charge operation, power consumption is high.
FIG. 3 illustrates a circuit diagram of another conventional semiconductor memory device having a charge transfer pre-sensing scheme. The semiconductor memory device of FIG. 3 includes first and second bit line isolation circuits 30 and 38, a pre-charge circuit 32, a PMOS sense amplifier 34 and an NMOS sense amplifier 36, and memory cells MCi and MCj. As in the memory device shown in FIG. 1, the memory cells MCi and MCj represent representative memory cells among memory cells arranged in a memory cell array block BLK1 and BLK2, respectively, among n-number of memory cell array blocks BLK1 to BLKn. Capacitor Cb1 represents a cell bit line load capacitor, and capacitor Csa represents a sense amplifier bit line load capacitor.
NMOS transistors N13 and N14 of the first bit line isolation circuit 30 are turned on in response to a control signal Vot to electrically connect the cell bit line pair BLcelli and BLBcelli to the sense amplifier bit line pair BLsa and BLBsa. NMOS transistors N15 to N17 of the pre-charge circuit 32 are turned on in response to a control signal BLPRE to pre-charge the cell bit line pair BLcelli and BLBcelli and the sense amplifier bit line pair BLsa and BLBsa to a voltage VBL. When a sense amplifier enable signal SAP having a voltage level Vcc is applied, PMOS transistors P3 and P4 of the PMOS sense amplifier 34 are turned on in response to a signal of the sense amplifier bit line pair BLsa and BLBsa having a logic xe2x80x9clowxe2x80x9d level to amplify a signal of the sense amplifier bit line pair BLsa and BLBsa having a logic xe2x80x9chighxe2x80x9d level to a voltage Vcc. When a sense amplifier enable signal SAN having a voltage level of 0 volts is applied, NMOS transistors N18 and N19 of the NMOS sense amplifier 36 are turned on in response to a signal of the sense amplifier bit line pair BLsa and BLBsa having a logic xe2x80x9chighxe2x80x9d level to amplify a signal of the sense amplifier bit line pair BLsa and BLBsa having a logic xe2x80x9clowxe2x80x9d level to a voltage of 0 volts. NMOS transistors N20 and N21 of the second bit line isolation circuit 38 are turned on in response to a control signal SG2 to electrically connect the cell bit line pair BLcellj and BLBcellj to the sense amplifier bit line pair BLsa and BLBsa.
Operation of the semiconductor memory device of FIG. 3 is described below with reference to the timing diagrams (A) and (B), as shown in FIG. 4. In particular, in FIG. 4, (A) is a timing diagram that relates to the operation of a cell bit line pair portion of the semiconductor memory device of FIG. 3, and (B) is a timing diagram that relates to the operation of a sense amplifier bit line pair of the semiconductor memory device of FIG. 3. In FIG. 4, a data is read from the memory cell array block BLK1.
During a time period t1, upon the application of a control signal Vot having a voltage level xe2x80x9cVcc+Vtnxe2x80x9d, a control signal BLPRE having a logic xe2x80x9chighxe2x80x9d level, and a voltage VBL having a level Vcc/2, the NMOS transistors N15, N16 and N17 are turned on to pre-charge the sense amplifier bit line pair BLsa and BLBsa to a voltage Vcc/2. The NMOS transistors N13 and N14 are turned on to transfer charges from the sense amplifier bit line pair BLsa and BLBsa to the cell bit line pair BLcelli and BLBcelli, thereby pre-charging the cell bit line pair BLcelli and BLBcelli to a voltage Vcc/2.
During a time period t2, when the control signal Vot having a voltage level of 0 volts and the voltage VBL having a voltage level Vcc(1+xcex3) are applied, the NMOS transistors N13 and N14 are turned off, such that the sense amplifier bit line pair BLsa and BLBsa is pre-charged to a voltage Vcc(1+xcex3). During a time period t3, when a high voltage VPP is applied to the word line WLi, NMOS transistor NM of the memory cell MCi is turned on, such that a voltage difference xcex94VBLcell occurs between the cell bit line pair BLcelli and BLBcelli.
During a time period t4, when the control signal Vot having a voltage level xe2x80x9cxcex2+Vtnxe2x80x9d is applied, the NMOS transistors N13 and N14 are turned on. A voltage of the cell bit line pair BLcelli and BLBcelli is raised to a voltage xcex2 (=Votxe2x88x92Vtn), such that a voltage difference between the cell bit line pair BLcelli and BLBcelli becomes 0 volts. A voltage of the sense amplifier bit line pair BLsa and BLBsa is steadily lowered, so that a voltage difference xcex94VBLsa occurs. During a time period t5, when a voltage difference of the cell bit line pair BLcelli and BLBcelli and the sense amplifier bit line pair BLsa and BLBsa is lowered below a threshold voltage Vtn of the NMOS transistors N13 and N14, the NMOS transistors N13 and N14 are turned off, thereby opening the connection between the cell bit line pair BLcelli and BLBcelli and the sense amplifier bit line pair BLsa and BLBsa.
During a time period t6, when the sense amplifier enable signals SAP and SAN, which have a voltage Vcc and a voltage of 0 volts respectively, are applied, the NMOS sense amplifier 34 and the PMOS sense amplifier 36 operate to amplify a voltage of the sense amplifier bit line pair BLsa and BLBsa to a voltage of Vcc and 0 volts, respectively. At this time, when the control signal Vot is transited to a voltage level xe2x80x9cVcc+Vtnxe2x80x9d, the NMOS transistors N13 and N14 are turned on, and the voltage of the sense amplifier bit line pair BLsa and BLBsa is transferred to the cell bit line pair BLcelli and BLBcelli. Therefore, a voltage of the cell bit line pair BLcelli and BLBcelli is also amplified to a voltage of Vcc and 0 volts, respectively.
However, the semiconductor memory device of FIG. 3 has a layout area size smaller than that of FIG. 1, and the voltage level of the control signal Vot applied to the NMOS transistors of the bit line isolation circuit has to be varied from Vcc+Vtn to 0 volts, from 0 volts to xcex2+Vtn, and from xcex2+Vtn to Vcc+Vtn, and a voltage level of the voltage VBL also has to be varied from Vcc/2 to Vcc(1+xcex3), and from Vcc(1+xcex3) to Vcc/2. Disadvantageously, it is also very difficult to accurately control such voltage levels.
In an effort to overcome the problems described above, it is a feature of an embodiment of the present invention to provide a semiconductor memory device and a bit line sensing method capable of controlling a bit line sensing operation without increasing a layout area size.
A preferred embodiment of the present invention provides a semiconductor memory device including a memory cell connected between a cell bit line pair and a word line; a bit line pre-charge circuit connected to the cell bit line pair for pre-charging the cell bit line pair to a voltage lower than a first voltage in response to a cell bit line pre-charge control signal; a sense amplifier bit line pre-charge circuit connected to a sense amplifier bit line pair for pre-charging the sense amplifier bit line pair to the first voltage in response to a sense amplifier bit line pre-charge control signal; a charge transfer circuit connected between the cell bit line pair and the sense amplifier bit line pair for transferring charges to the cell bit line pair and the sense amplifier bit line pair in response to a control signal; a first sense amplifier circuit connected between the sense amplifier bit line pair for amplifying a voltage of the sense amplifier bit line pair to the first voltage; and a second sense amplifier circuit connected between the sense amplifier bit line pair for amplifying a voltage of the sense amplifier bit line pair to a second voltage in response to a sense amplifier enable signal.
The control signal may be maintained at the second voltage, and may be transited to the first voltage before the sense amplifier enable signal is generated after an active command is applied, and may be transited from the first voltage to a third voltage after the sense amplifier enable signal is generated. The control signal is generated by a signal generating circuit and a control signal, wherein the signal generating circuit preferably includes: a first delay circuit having the same line load as a word line enable signal for enabling the word line, and receiving and delaying the active command; a second delay circuit delaying an output signal of the first delay circuit by a first time to generate a first signal; and a third delay circuit delaying the output signal of the first delay circuit by a second time to generate a second signal, wherein the control signal generating circuit generates the control signal having the first voltage in response to the first signal, and generates the control signal having the third voltage in response to the second signal.
The voltage lower than the first voltage is preferably the first voltage/2. The first voltage may be an internal or an external power voltage. The second voltage may be a ground voltage. The third voltage may be a high voltage higher than the power voltage.
The sense amplifier bit line pre-charge circuit preferably includes first and second PMOS transistors serially connected between the sense amplifier bit line pair and having a common source receiving the first voltage and a gate receiving the sense amplifier bit line pre-charge control signal. The first sense amplifier circuit preferably includes third and fourth PMOS transistors serially connected between the sense amplifier bit line pair and having a gate connected to the sense amplifier bit line pair and a common source receiving the first voltage. The first sense amplifier circuit preferably includes third and fourth PMOS transistors serially connected between the sense amplifier bit line pair and having a gate connected to the sense amplifier bit line pair and a common source receiving the first voltage in response to the sense amplifier enable signal. The second sense amplifier circuit preferably includes first and second NMOS transistors serially connected between the sense amplifier bit line pair and having a gate connected to the sense amplifier bit line pair and a common source receiving the second voltage in response to the sense amplifier enable signal.
A preferred embodiment of the present invention also provides a bit line sensing method of a semiconductor memory device including separating a cell bit line pair from a sense amplifier bit line pair when a control signal of a first voltage is applied, pre-charging the cell bit line pair to a voltage lower than the first voltage, and pre-charging the sense amplifier bit line pair to the first voltage when a sense amplifier bit line pre-charge control signal is applied; generating a voltage difference between the cell bit line pair by enabling a word line and selecting a memory cell; generating a first voltage difference between the cell bit line pair by connecting the cell bit line pair to the sense amplifier bit line pair when the control signal having the second voltage is applied, and generating a second voltage difference between the sense amplifier bit line pair by reducing a voltage of the sense amplifier bit line pair; maintaining a voltage of the cell bit line pair and the sense amplifier bit line pair to a certain voltage; and amplifying the sense amplifier bit line pair to the first voltage and the second voltage by enabling the PMOS sense amplifier and the NMOS sense amplifier, and transferring a voltage of the sense amplifier bit line pair to the cell bit line pair when the control signal having the third voltage is applied.
The voltage lower than the first voltage may be the first voltage/2. The first voltage may be an internal power voltage or an external power voltage. The second voltage may be a ground voltage. The third voltage may be a high voltage higher the power voltage.